	US 12,268,097 B2
	Top-interconnection metal lines for a memory array device and methods for forming the same
Yu-Feng Yin, Hsinchu (TW); Tai-Yen Peng, Hsinchu (TW); An-Shen Chang, Jubei (TW); Qiang Fu, Hsinchu (TW); Chung-Te Lin, Taiwan (TW); and Han-Ting Tsai, Kaoshiung (TW)
Assigned to Taiwan Semiconductor Manufacturing Company Limited, Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company Limited, Hsinchu (TW)
Filed on Jun. 16, 2023, as Appl. No. 18/336,430.
Application 18/336,430 is a division of application No. 17/224,309, filed on Apr. 7, 2021, granted, now 11,723,284.
Claims priority of provisional application 63/039,529, filed on Jun. 16, 2020.
Prior Publication US 2023/0329123 A1, Oct. 12, 2023
Int. Cl. H10N 50/10 (2023.01); H01L 23/528 (2006.01); H10B 61/00 (2023.01); H10N 50/01 (2023.01); H10N 50/80 (2023.01)

CPC H10N 50/10 (2023.02) [H01L 23/5283 (2013.01); H10B 61/22 (2023.02); H10N 50/01 (2023.02); H10N 50/80 (2023.02)]

20 Claims

1. A method of manufacturing a memory array device, comprising;

forming an array of memory cells over a substrate by depositing and patterning a memory material layer stack, wherein each of the memory cells comprises, from bottom to top, a bottom electrode, a memory element, and a top electrode;

forming a memory-level dielectric layer around the array of memory cells;

planarizing the top electrodes of the array of memory cells by removing portions of the top electrodes from above a horizontal plane located above bottom surfaces of the top electrodes; and

forming top-interconnection metal lines by depositing and patterning a conductive material above the memory-level dielectric layer, wherein the top-interconnection metal lines are formed on, or replaces, a respective row of top electrodes within the memory cells.