CPC H10N 50/10 (2023.02) [H10B 61/20 (2023.02); H10N 50/01 (2023.02); H10N 50/80 (2023.02); H10N 50/85 (2023.02)] | 20 Claims |
11. A semiconductor device, comprising:
an interconnect layer comprising a first dielectric layer and a conductive structure;
first and second magnetic tunnel junction (MTJ) structures disposed on the interconnect layer, wherein the first and second MTJ structures comprise first and second sidewalls, respectively, facing each other; and
a spacer stack disposed between the first and second MTJ structures, wherein the spacer stack comprises:
first and second nitride layers disposed on the first and second sidewalls, respectively;
a continuous metal-based layer disposed on the first and second nitride layers; and
a second dielectric layer disposed on the continuous metal-based layer.
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