US 12,268,066 B2
Display panel, method of manufacturing the same and display device
Yipeng Chen, Beijing (CN); Lujiang Huangfu, Beijing (CN); and Libin Liu, Beijing (CN)
Assigned to BOE Technology Group Co., Ltd., Beijing (CN)
Appl. No. 17/762,697
Filed by BOE Technology Group Co., Ltd., Beijing (CN)
PCT Filed Apr. 15, 2021, PCT No. PCT/CN2021/087371
§ 371(c)(1), (2) Date Mar. 22, 2022,
PCT Pub. No. WO2021/227761, PCT Pub. Date Nov. 18, 2021.
Claims priority of application No. 202010387399.9 (CN), filed on May 9, 2020.
Prior Publication US 2022/0406874 A1, Dec. 22, 2022
Int. Cl. H01L 27/32 (2006.01); H10K 59/121 (2023.01); H10K 59/131 (2023.01); H10K 71/00 (2023.01); H10K 59/12 (2023.01)
CPC H10K 59/131 (2023.02) [H10K 59/1216 (2023.02); H10K 71/00 (2023.02); H10K 59/1201 (2023.02)] 14 Claims
OG exemplary drawing
 
1. A display panel, comprising: a substrate, and an initialization signal line layer and an anode layer sequentially stacked on the substrate along a direction away from the substrate, and a plurality of sub-pixel areas arranged in an array; wherein
the initialization signal line layer includes an initialization signal line pattern arranged in each of the plurality of sub-pixel areas;
the anode layer includes a plurality of anode patterns corresponding to the plurality of sub-pixel areas in a one-to-one manner, the plurality of anode patterns are arranged at intervals, and an anode spacing area is formed between adjacent anode patterns;
the display panel further includes: a first auxiliary signal line layer, the first auxiliary signal line layer has a grid structure, and at least part of the first auxiliary signal line layer is located in the anode spacing area and is insulated from the anode pattern, and the initialization signal line pattern in each of plurality of the sub-pixel areas is coupled to the first auxiliary signal line layer;
wherein the display panel further comprises:
a power supply signal line layer located between the initialization signal line layer and the anode layer, wherein the power supply signal line layer includes a power signal line pattern arranged in each of the plurality of sub-pixel areas, and at least part of the power signal line pattern extends along a second direction; and
a second auxiliary signal line layer located between the initialization signal line layer and the power supply signal line layer, wherein the second auxiliary signal line layer includes second auxiliary signal line patterns corresponding to the plurality of sub-pixel areas in a one-to-one manner, a third overlapping area is formed between orthographic projection of the power signal line pattern on the substrate and orthographic projection of a corresponding second auxiliary signal line pattern on the substrate, the second auxiliary signal line pattern is coupled to the power signal line pattern in the third overlapping area, orthographic projection of the second auxiliary signal line pattern on the substrate overlaps orthographic projection of the corresponding initialization signal line pattern on the substrate;
wherein the second auxiliary signal line pattern includes a first portion extending along the first direction and a second portion extending along the second direction, the first direction intersects the second direction;
the initialization signal line pattern includes a third portion extending along the first direction and a fourth portion extending along the second direction, and orthographic projection of the first portion on the substrate overlaps orthographic projection of the third portion on the substrate, and orthographic projection of the second portion on the substrate overlaps orthographic projection of the fourth portion on the substrate.