| CPC H10K 59/131 (2023.02) [H01L 25/18 (2013.01); H10K 59/40 (2023.02); H10K 77/111 (2023.02)] | 15 Claims |
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1. A display panel, comprising:
an active area in which a plurality of pixels is disposed;
a non-active area including a plurality of pads connected to the active area,
wherein the plurality of pads includes a first pad and a second pad which are separated from each other by a first distance in a first direction, a third pad which is separated from the first pad and the second pad by a second distance in a second direction, wherein the first pad and the second pad are disposed on a device region for an integrated circuit;
a link line extending from a first end of the link line to a second end in the second direction, wherein the link line is disposed between the first pad and the second pad and connected to the third pad disposed in a test interface region, and wherein the first end of the link line is coupled to the third pad; and
a metal layer disposed over the link line in the device region and between the first pad and the second pad,
wherein at least one of the first pad, the second pad, and the third pad includes a gate metal layer, an insulating layer, a first metal layer, a second metal layer, a sensor metal layer, and a buffer layer, and
wherein the metal layer disposed on the link line includes a same material as the first metal layer or the second metal layer.
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