| CPC H10K 59/124 (2023.02) [H10K 50/86 (2023.02); H10K 71/00 (2023.02); H10K 59/1201 (2023.02); H10K 59/122 (2023.02)] | 20 Claims |

|
1. A display panel comprising:
a substrate;
a transistor on the substrate;
a planarization layer on the transistor, and defining at least one recess;
a first pixel electrode and a second pixel electrode on the planarization layer, with the recess therebetween in a plan view;
a metal pattern on the planarization layer, and adjacent to the first pixel electrode or the second pixel electrode;
a pixel defining layer on the metal pattern and filling the recess; and
a spacer on the pixel defining layer and overlapping with the metal pattern.
|