CPC H10K 50/8445 (2023.02) [H10K 50/8428 (2023.02); H10K 59/40 (2023.02)] | 5 Claims |
1. A display device comprising:
a substrate including a display region and a peripheral region surrounding the display region;
a transistor in the display region;
a leveling film covering the transistor in the display region;
a pixel electrode arranged on the leveling film and electrically connected to the transistor;
a partition wall covering an edge portion of the pixel electrode;
a counter electrode covering the pixel electrode and the partition wall;
an EL layer arranged between the pixel electrode and the counter electrode; and
at least one dam arranged in the peripheral region, wherein
the dam surrounds the display region and is spaced away from the leveling film,
the dam comprises a first layer in a same layer as the leveling film, a second layer in a same layer as the partition wall, and a stopper on and in contact with the second layer,
the stopper contains an inorganic material, and
a part of an upper surface of the second layer is exposed from the stopper.
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