US 12,268,042 B2
Variable resistance memory device
Hyuncheol Kim, Seoul (KR); Yongseok Kim, Suwon-si (KR); Dongsoo Woo, Seoul (KR); and Kyunghwan Lee, Seoul (KR)
Assigned to Samsung Electronics Co., Ltd., Gyeonggi-do (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on May 17, 2022, as Appl. No. 17/746,247.
Claims priority of application No. 10-2021-0130739 (KR), filed on Oct. 1, 2021.
Prior Publication US 2023/0108552 A1, Apr. 6, 2023
Int. Cl. H01L 21/00 (2006.01); H10K 10/50 (2023.01); H10K 19/00 (2023.01); H10K 85/20 (2023.01)
CPC H10K 19/202 (2023.02) [H10K 10/50 (2023.02); H10K 85/221 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A variable resistance memory device, comprising:
a stack including insulating sheets and conductive sheets, which are alternatingly stacked on a substrate, the stack including a vertical hole vertically penetrating therethrough;
a bit line on the stack;
a conductive pattern electrically connected to the bit line and vertically extending in the vertical hole; and
a resistance varying layer between the conductive pattern and an inner side surface of the stack defining the vertical hole,
wherein the resistance varying layer comprises a first carbon nanotube electrically connected to the conductive sheets, and a second carbon nanotube electrically connected to the conductive pattern.