US 12,268,032 B2
Electrostatic protection circuit and semiconductor device
Tsutomu Tomioka, Nagano (JP)
Assigned to ABLIC Inc., Nagano (JP)
Filed by ABLIC Inc., Nagano (JP)
Filed on Sep. 13, 2023, as Appl. No. 18/466,492.
Application 18/466,492 is a division of application No. 17/112,070, filed on Dec. 4, 2020, granted, now 11,791,330.
Claims priority of application No. 2019-233133 (JP), filed on Dec. 24, 2019.
Prior Publication US 2024/0006408 A1, Jan. 4, 2024
Int. Cl. H10D 89/60 (2025.01); H02H 9/04 (2006.01)
CPC H10D 89/921 (2025.01) [H02H 9/046 (2013.01); H10D 89/611 (2025.01); H10D 89/811 (2025.01); H10D 89/817 (2025.01); H10D 89/911 (2025.01)] 4 Claims
OG exemplary drawing
 
1. An electrostatic protection circuit configured to protect a signal terminal of an internal circuit of a semiconductor device, comprising:
a first diode having an anode connected to the signal terminal;
a second diode having a cathode connected to a cathode of the first diode and an anode connected to a GND terminal;
a depletion type MOS transistor connected in parallel with the first diode, wherein the depletion type MOS transistor is an nMOS transistor having a gate, a source, and a bulk connected to the internal circuit, and having a drain connected to the cathode of the first diode; and
a first resistor connected between the anode of the first diode and the gate of the nMOS transistor.