US 12,268,031 B2
Backside power rails and power distribution network for density scaling
Ruilong Xie, Niskayuna, NY (US); Kisik Choi, Watervliet, NY (US); Somnath Ghosh, Clifton Park, NY (US); Sagarika Mukesh, Albany, NY (US); Albert Chu, Nashua, NH (US); Albert M. Young, Fishkill, NY (US); Balasubramanian S. Pranatharthiharan, Santa Clara, CA (US); Huiming Bu, Glenmont, NY (US); Kai Zhao, Albany, NY (US); John Christopher Arnold, North Chatham, NY (US); Brent A. Anderson, Jericho, VT (US); and Dechao Guo, Niskayuna, NY (US)
Assigned to International Business Machines Corporation, Armonk, NY (US)
Filed by International Business Machines Corporation, Armonk, NY (US)
Filed on Dec. 27, 2021, as Appl. No. 17/562,331.
Prior Publication US 2023/0207553 A1, Jun. 29, 2023
Int. Cl. H10D 89/10 (2025.01); H01L 21/762 (2006.01); H10D 30/67 (2025.01); H10D 62/10 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01); H10D 84/85 (2025.01); H10D 86/40 (2025.01); H10D 86/60 (2025.01)
CPC H10D 89/10 (2025.01) [H01L 21/76229 (2013.01); H10D 30/6735 (2025.01); H10D 62/121 (2025.01); H10D 84/0149 (2025.01); H10D 84/038 (2025.01); H10D 84/85 (2025.01); H10D 86/471 (2025.01); H10D 86/60 (2025.01)] 12 Claims
OG exemplary drawing
 
1. A device comprising:
a first cell comprising a first transistor;
a second cell comprising a second transistor, wherein the first and second cells are disposed adjacent to each other with the first and second transistors disposed adjacent to each other; and
an isolation structure disposed in a cell boundary region between the first and second cells;
wherein the isolation structure comprises a first portion disposed above first and second active channel structures of the respective first and second transistors, and a second portion disposed between the first and second active channel structures;
wherein the first portion of the isolation structure comprises a first width which is substantially equal to a spacing between the first and second active channel structures;
wherein the second portion of the isolation structure comprises a second width which is less than the first width;
wherein a first space between the second portion of the isolation structure and the first active channel structures of the first transistor comprises metallic material of a first metal gate structure of the first transistor, and a second space between the second portion of the isolation structure and the second active channel structures of the second transistor comprises metallic material of a second metal gate structure of the second transistor; and
wherein the first space and the second space define respective gate extension lengths of the first and second transistors.