US 12,268,027 B2
Middle-of-line interconnect structure and manufacturing method
Yu-Lien Huang, Jhubei (TW); Ching-Feng Fu, Taichung (TW); and Huan-Just Lin, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Aug. 4, 2023, as Appl. No. 18/365,503.
Application 18/365,503 is a division of application No. 17/134,830, filed on Dec. 28, 2020.
Claims priority of provisional application 63/081,423, filed on Sep. 22, 2020.
Prior Publication US 2023/0378291 A1, Nov. 23, 2023
Int. Cl. H01L 21/8234 (2006.01); H01L 27/088 (2006.01); H10D 64/23 (2025.01); H10D 64/27 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01); H10D 84/83 (2025.01); H01L 29/417 (2006.01); H01L 29/423 (2006.01)
CPC H10D 64/258 (2025.01) [H10D 64/513 (2025.01); H10D 64/514 (2025.01); H10D 84/013 (2025.01); H10D 84/0144 (2025.01); H10D 84/0149 (2025.01); H10D 84/038 (2025.01); H10D 84/83 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A method for fabricating an integrated circuit device,
the method comprising:
forming a pair of source/drain regions over a substrate and a gate electrode between the pair of source/drain regions;
forming a lower inter-layer dielectric (ILD) layer over the pair of source/drain regions and surrounding the gate electrode;
etching back the gate electrode to form a recess region from top of the lower ILD layer;
forming a gate capping layer on the gate electrode within the recess region;
forming a lower source/drain contact on a source/drain region of the pair of source/drain regions;
forming a source/drain capping layer on the lower source/drain contact;
forming a gate electrode contact through the gate capping layer and reaching on the gate electrode; and
forming a contact structure comprising a first portion and a second portion, wherein the first portion is disposed through the gate capping layer, and wherein the second portion is disposed through the source/drain capping layer.