CPC H10D 64/258 (2025.01) [H10D 64/513 (2025.01); H10D 64/514 (2025.01); H10D 84/013 (2025.01); H10D 84/0144 (2025.01); H10D 84/0149 (2025.01); H10D 84/038 (2025.01); H10D 84/83 (2025.01)] | 20 Claims |
1. A method for fabricating an integrated circuit device,
the method comprising:
forming a pair of source/drain regions over a substrate and a gate electrode between the pair of source/drain regions;
forming a lower inter-layer dielectric (ILD) layer over the pair of source/drain regions and surrounding the gate electrode;
etching back the gate electrode to form a recess region from top of the lower ILD layer;
forming a gate capping layer on the gate electrode within the recess region;
forming a lower source/drain contact on a source/drain region of the pair of source/drain regions;
forming a source/drain capping layer on the lower source/drain contact;
forming a gate electrode contact through the gate capping layer and reaching on the gate electrode; and
forming a contact structure comprising a first portion and a second portion, wherein the first portion is disposed through the gate capping layer, and wherein the second portion is disposed through the source/drain capping layer.
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