US 12,268,025 B1
ALEFT-ISD-LTSEE{Advanced Low Electrostatic Field Transistor using Implanted S/D and Low Temperature Selective Epitaxial Extension}
Mammen Thomas, Seattle, WA (US)
Filed by Mammen Thomas, Seattle, WA (US)
Filed on May 14, 2024, as Appl. No. 18/663,423.
Int. Cl. H01L 21/02 (2006.01); H10D 30/60 (2025.01); H10D 62/10 (2025.01); H10D 62/13 (2025.01); H10D 62/17 (2025.01)
CPC H10D 62/314 (2025.01) [H10D 30/601 (2025.01); H10D 62/102 (2025.01); H10D 62/116 (2025.01); H10D 62/151 (2025.01)] 19 Claims
OG exemplary drawing
 
1. A transistor structure for advanced Low Electrostatic Field Transistor that enables a gate length and a corresponding length of a device channel to be defined and scaled using two self-aligned low temperature selective epitaxial extension depositions on a surface of a semiconductor substrate or on a surface of a well in the semiconductor substrate; wherein the device channel is established in the semiconductor under a gate dielectric on the surface of the semiconductor substrate or the surface of the well in the semiconductor substrate;
wherein the use of the use of the selective epitaxial extension depositions on a surface of the semiconductor substrate or on the surface of the well in the semiconductor substrate eliminate source and drain extension implants close to or abutting the device channel;
wherein the selective epitaxial extension depositions on the surface of the semiconductor substrate or the surface of the well in the semiconductor substrate are in contact with a shallow source/drain implant into the surface of the semiconductor substrate or the surface of the well in the semiconductor substrate; wherein the shallow source/drain implant is spaced away from the device channel; and
wherein the selective epitaxial extension depositions also connect to the source/drain silicide contact.