US 12,268,023 B2
Devices with improved operational current and reduced leakage current
Po-Yu Lin, Hsinchu (TW); Tzu-Hua Chiu, Hsinchu (TW); Wei-Yang Lee, Taipei (TW); Chia-Pin Lin, Hsinchu County (TW); and Yuan-Ching Peng, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Aug. 31, 2021, as Appl. No. 17/462,869.
Prior Publication US 2023/0063612 A1, Mar. 2, 2023
Int. Cl. H01L 29/06 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 29/786 (2006.01); H10D 30/01 (2025.01); H10D 30/67 (2025.01); H10D 62/10 (2025.01); H10D 64/01 (2025.01)
CPC H10D 62/121 (2025.01) [H10D 30/031 (2025.01); H10D 30/6713 (2025.01); H10D 30/6735 (2025.01); H10D 30/6757 (2025.01); H10D 64/018 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a source/drain feature over a semiconductor substrate;
channel layers connected to the source/drain feature;
a gate structure between adjacent channel layers and wrapping the channel layers; and
an inner spacer between the source/drain feature and the gate structure and between adjacent channel layers,
wherein the source/drain feature has a first interface with a first channel layer of the channel layer, and the first interface has a convex profile protruding towards the first channel layer, and
wherein a height of the inner spacer is greater than a distance between the adjacent channel layers.