US 12,268,017 B2
Shielded gate trench MOSFETs with improved trench terminations and shielded gate trench contacts
Fu-Yuan Hsieh, New Taipei (TW)
Assigned to NAMI MOS CO., LTD., New Taipei (TW)
Filed by NAMI MOS CO., LTD., New Taipei (TW)
Filed on Jun. 10, 2022, as Appl. No. 17/837,502.
Application 17/837,502 is a continuation in part of application No. 17/729,460, filed on Apr. 26, 2022.
Prior Publication US 2023/0343867 A1, Oct. 26, 2023
Int. Cl. H10D 30/66 (2025.01); H10D 62/10 (2025.01); H10D 62/17 (2025.01); H10D 64/00 (2025.01)
CPC H10D 30/665 (2025.01) [H10D 30/668 (2025.01); H10D 62/112 (2025.01); H10D 62/393 (2025.01); H10D 64/117 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A shielded gate trench (SGT) device comprising:
an active area, a termination area, a gate metal pad area, a central gate metal runner and at least one shielded gate trench contact row area;
said active area comprising a plurality of gate trenches formed in an epitaxial layer of a first conductivity type onto a substrate of said first conductivity type along a first axis including a first type active trenches having a first active trench length, and a second type active trenches near the said gate metal pad area having a second active trench length, wherein said first active trench length is longer than the second active trench length;
said termination area comprising at least one first termination trench surrounding outer periphery of said plurality of gate trenches in a first direction along said first axis and in a second direction along a second axis wherein said first axis is vertical to said second axis, and said at least one first type termination trench is separated from said plurality of gate trenches and does not surround said gate metal pad area;
said plurality of gate trenches are formed in said active area, surrounded by a first type source regions of said first conductivity type encompassed in a first type body regions of a second conductivity type near a top surface of said epitaxial layer of said first conductivity type, each of said plurality of gate trenches is filled with a gate electrode and a shielded gate electrode; said shielded gate electrode is insulated from said epitaxial layer by a first insulating film, said gate electrode is insulated from said epitaxial layer by a gate oxide, said shielded gate electrode and said gate electrode are insulated from each other by an (Inter-Poly Oxide) IPO film, said gate oxide surrounds said gate electrode and has less thickness than said first insulating film;
said gate electrode inside each of said gate trenches is connected to said gate metal pad area through said central gate metal runner having a plurality of gate trench contacts underneath;
said shielded gate electrode inside each of said gate trenches is connected to a source metal through at least one shielded gate trench contact on each of said plurality of gate trenches, said at least one shielded gate trench contact locates in said at least one shielded gate contact row area along said second axis, and said at least one shield gate trench contact is spaced apart from said gate metal runner with a distance larger than 100 μm, and said central gate metal runner is disposed in the vicinity of the middle of said source metal.