US 12,268,011 B2
Pillar select transistor for 3-dimensional cross point memory
Prashant Majhi, San Jose, CA (US); Derchang Kau, Cupertino, CA (US); and Max Hineman, Boise, ID (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Dec. 10, 2020, as Appl. No. 17/118,385.
Prior Publication US 2022/0190030 A1, Jun. 16, 2022
Int. Cl. H01L 27/00 (2006.01); G11C 5/06 (2006.01); G11C 13/00 (2006.01); H01L 27/06 (2006.01); H10B 63/00 (2023.01); H10N 70/00 (2023.01); H10N 70/20 (2023.01)
CPC H10B 63/845 (2023.02) [G11C 5/06 (2013.01); G11C 13/0002 (2013.01); H01L 27/0688 (2013.01); H10N 70/021 (2023.02); H10N 70/253 (2023.02); H10N 70/883 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A memory device structure, comprising:
a transistor, comprising:
a channel between a source and a drain, the channel along a longitudinal axis of the transistor, the channel comprising vertical portions on opposing sidewalls of one of the source or the drain and a horizontal portion on the other of the source or the drain;
a gate electrode along a first direction orthogonal to the longitudinal axis; and
a gate dielectric layer between the gate electrode and the channel;
a first interconnect coupled with the one of the source or the drain, the first interconnect colinear with the channel;
a pair of second interconnects along a second direction orthogonal to both the longitudinal axis and the first direction; and
a pair of memory cells, wherein individual ones of the pair of memory cells comprises a selector element and a memory element, wherein a first terminal of the individual ones of the pair of memory cells is coupled to the first interconnect and wherein a second terminal of the individual ones of the pair of memory cells is coupled to individual ones of the pair of second interconnects.