US 12,268,009 B2
Memory device including vertical stack structure, method of fabricating the same, and electronic device including memory device
Yumin Kim, Seoul (KR); Doyoon Kim, Hwaseong-si (KR); Seyun Kim, Seoul (KR); Hyunjae Song, Hwaseong-si (KR); and Seungyeul Yang, Hwaseong-si (KR)
Assigned to Samsung Electronics Co., Ltd., Gyeonggi-do (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Mar. 3, 2022, as Appl. No. 17/685,942.
Claims priority of application No. 10-2021-0126711 (KR), filed on Sep. 24, 2021.
Prior Publication US 2023/0093892 A1, Mar. 30, 2023
Int. Cl. H10B 63/00 (2023.01); H10N 70/00 (2023.01); H10N 70/20 (2023.01)
CPC H10B 63/34 (2023.02) [H10B 63/84 (2023.02); H10B 63/845 (2023.02); H10N 70/066 (2023.02); H10N 70/24 (2023.02); H10N 70/8265 (2023.02); H10N 70/8833 (2023.02); H10N 70/881 (2023.02)] 40 Claims
OG exemplary drawing
 
1. A memory device comprising:
a base substrate;
an oxygen scavenger layer on the base substrate;
a recording material layer on the oxygen scavenger layer, the recording material layer being in direct contact with the oxygen scavenger layer;
a channel layer on the recording material layer;
a gate insulating layer on the channel layer; and
a gate electrode on the gate insulating layer,
wherein the oxygen scavenger layer comprises an element that forms oxygen vacancies in the recording material layer and does not comprise oxygen.