US 12,268,007 B2
Memory device including etch stop pattern and method of forming the same
Meng-Han Lin, Hsinchu (TW); Han-Jong Chia, Hsinchu (TW); and Feng-Cheng Yang, Hsinchu County (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Jan. 12, 2022, as Appl. No. 17/574,518.
Prior Publication US 2023/0225131 A1, Jul. 13, 2023
Int. Cl. H10B 51/20 (2023.01); H01L 29/24 (2006.01); H01L 29/417 (2006.01); H10B 51/10 (2023.01)
CPC H10B 51/20 (2023.02) [H01L 29/24 (2013.01); H01L 29/41741 (2013.01); H01L 29/41775 (2013.01); H10B 51/10 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A memory device, comprising:
a first etch stop layer;
an etch stop pattern in the first etch stop layer;
a second etch stop layer on the first etch stop layer and the etch stop pattern, wherein a material of the etch stop pattern is different from a material of the first etch stop layer and a material of the second etch stop layer, and the materials of the etch stop pattern, the first etch stop layer and the second etch stop layer are dielectric materials;
a plurality of stacks, disposed on the second etch stop layer; and
a first conductive pillar between the stacks, wherein the first conductive pillar extends along the stacks and the second etch stop layer to be in physical contact with the etch stop pattern.