US 12,268,003 B2
Vertical memory devices
Kohji Kanamori, Suwon-si (KR); and Shinhwan Kang, Suwon-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Sep. 20, 2023, as Appl. No. 18/370,543.
Application 18/370,543 is a division of application No. 17/705,513, filed on Mar. 28, 2022, granted, now 11,778,826.
Application 17/705,513 is a continuation of application No. 16/853,047, filed on Apr. 20, 2020, granted, now 11,289,507, issued on Mar. 29, 2022.
Claims priority of application No. 10-2019-0131640 (KR), filed on Oct. 22, 2019.
Prior Publication US 2024/0015968 A1, Jan. 11, 2024
Int. Cl. H10B 43/27 (2023.01); H01L 21/02 (2006.01); H01L 21/28 (2006.01); H01L 21/311 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H10B 43/10 (2023.01); H10B 43/40 (2023.01); H10B 43/50 (2023.01)
CPC H10B 43/27 (2023.02) [H01L 21/02532 (2013.01); H01L 21/02592 (2013.01); H01L 21/02636 (2013.01); H01L 21/02667 (2013.01); H01L 21/31111 (2013.01); H01L 21/31116 (2013.01); H01L 21/31144 (2013.01); H01L 23/5226 (2013.01); H01L 23/528 (2013.01); H01L 29/40117 (2019.08); H10B 43/10 (2023.02); H10B 43/40 (2023.02); H10B 43/50 (2023.02)] 7 Claims
OG exemplary drawing
 
1. A vertical memory device, comprising:
a substrate;
gate electrodes spaced apart from each other on the substrate in a first direction substantially perpendicular to an upper surface of the substrate, the gate electrodes being stacked to have a staircase shape in a staircase region, and each of the gate electrodes extending in a second direction substantially parallel to the upper surface of the substrate;
a channel disposed in a memory region and extending through the gate electrodes in the first direction; and
first contact plugs disposed in the staircase region to be spaced apart from the channel in the second direction;
wherein the gate electrodes include a plurality of first gate electrodes and a plurality of second gate electrodes between the plurality of first gate electrodes and the substrate, respectively,
wherein each of the first contact plugs extends through a pad of a corresponding one of the gate electrodes and is electrically connected to the corresponding one of the gate electrodes,
wherein a number of a first set of gate electrodes of the plurality of second gate electrodes through which a first one of the first contact plugs extends is equal to or more than a number of a second set of gate electrodes of the plurality of second gate electrodes through which a second one of the first contact plugs extends,
wherein the first one of the first contact plugs extends through a pad of one gate electrode of the first set of gate electrodes to be electrically connected to the one gate electrode of the first set of gate electrodes,
wherein the second one of the first contact plugs extends through a pad of one gate electrode of the second set of gate electrodes to be electrically connected to the one gate electrode of the second set of the electrodes, and
wherein the one gate electrode of the second set of gate electrodes is between the substrate and the one gate electrode of the first set of gate electrodes.