CPC H10B 43/27 (2023.02) [H10B 43/10 (2023.02); H10B 43/35 (2023.02); H10B 43/40 (2023.02); H10B 43/50 (2023.02)] | 12 Claims |
1. A semiconductor memory device, comprising:
a substrate;
a first conductor layer including silicon and being provided above the substrate;
a second conductor layer including silicon and being provided on and in contact with the first conductor layer;
a first stacked body provided above the second conductor layer, including a plurality of first electrode layers stacked apart from each other in a first direction;
a columnar portion penetrating the first stacked body in the first direction and including a semiconductor layer;
a layered member provided between the substrate and the first stacked body, including a fourth conductor layer including silicon, the layered member provided in a plane providing the first conductor layer, the layered member provided separately from the first conductor layer in the plane, and a height of a lower surface of the fourth conductor layer being as same as a height of a lower surface of the first conductor layer in the first direction;
a first insulating layer provided between the layered member and a lowermost electrode layer of the plurality of first electrode layers; and
a first insulating member penetrating the first stacked body in the first direction and extending in a second direction crossing the first direction in the first stacked body and dividing the first stacked body in a third direction crossing the first direction and the second direction, wherein the semiconductor layer penetrates the second conductor layer and a lower end of the semiconductor layer is located in and in contact with the first conductor layer,
the first insulating member penetrates the first insulating layer and has a lower end which locates in the layered member.
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