	US 12,267,999 B2
	3-dimensional NAND memory with reduced thermal budget
SungHae Lee, Suwon-si (KR)
Assigned to ENTEGRIS, INC., Billerica, MA (US)
Appl. No. 17/626,446
Filed by ENTEGRIS, INC., Billerica, MA (US)
PCT Filed Jul. 13, 2020, PCT No. PCT/US2020/041820 § 371(c)(1), (2) Date Jan. 11, 2022, PCT Pub. No. WO2021/015978, PCT Pub. Date Jan. 28, 2021.
Claims priority of provisional application 62/876,120, filed on Jul. 19, 2019.
Prior Publication US 2022/0246639 A1, Aug. 4, 2022
Int. Cl. H10B 43/35 (2023.01); H10B 43/27 (2023.01); H10B 43/40 (2023.01)

CPC H10B 43/27 (2023.02) [H10B 43/35 (2023.02); H10B 43/40 (2023.02)]

19 Claims

1. A method of manufacturing a NAND memory device, comprising:

depositing a channel layer;

depositing a tunnel dielectric layer;

depositing a trap layer;

depositing a first blocking layer comprising SiO₂;

depositing a second blocking layer comprising MgO on the first blocking layer;

annealing the second blocking layer;

depositing barrier metal on the second blocking layer; and

depositing a word line material on the barrier metal.