US 12,267,996 B2
DRAM sense amplifier architecture with reduced power consumption and related methods
Richard Stephen Roy, Lago Vista, TX (US); and Robert J. Mears, Wellesley, MA (US)
Assigned to Atomera Incorporated, Los Gatos, CA (US)
Filed by Atomera Incorporated, Los Gatos, CA (US)
Filed on May 3, 2023, as Appl. No. 18/311,465.
Claims priority of provisional application 63/366,262, filed on Jun. 13, 2022.
Claims priority of provisional application 63/364,120, filed on May 4, 2022.
Prior Publication US 2023/0363150 A1, Nov. 9, 2023
Int. Cl. G11C 11/24 (2006.01); G11C 11/406 (2006.01); G11C 11/4091 (2006.01); H01L 25/065 (2023.01); H10B 12/00 (2023.01); H10B 80/00 (2023.01)
CPC H10B 12/50 (2023.02) [G11C 11/406 (2013.01); G11C 11/4091 (2013.01); H01L 25/0657 (2013.01); H10B 80/00 (2023.02)] 26 Claims
OG exemplary drawing
 
1. A dynamic random access memory (DRAM) device comprising:
a DRAM cell comprising a capacitor and a bit cell pass gate transistor coupling the capacitor to a bit line;
a single-ended sense amplifier comprising:
a cross-coupled transistor sensing circuit comprising a first p-channel transistor coupled between a first terminal and a first line, a first n-channel transistor coupled between the first line and a second terminal, the first p-channel transistor and the first n-channel transistor each having a gate coupled to a second line, a second p-channel transistor coupled between the first terminal and the second line, and a second n-channel transistor coupled between the second terminal and the second line, the second p-channel transistor and the second n-channel transistor each having a gate coupled to the first line;
a precharge circuit configured to selectively provide a first reference voltage and a second reference voltage to the first line and the second line, respectively;
a refresh circuit configured to selectively apply a third reference voltage to the bit line, wherein the refresh circuit is controlled by a voltage on the second line; and
a bit line transistor directly coupling the bit line to the first line of the cross-coupled transistor sensing circuit, wherein the bit line is the only bit line coupled to the cross-coupled transistor sensing circuit.