US 12,267,993 B2
Semiconductor structure having buried word lines
Min-Chung Cheng, Taoyuan (TW)
Assigned to NANYA TECHNOLOGY CORPORATION, New Taipei (TW)
Filed by NANYA TECHNOLOGY CORPORATION, New Taipei (TW)
Filed on Jun. 30, 2023, as Appl. No. 18/216,775.
Application 18/216,775 is a division of application No. 17/201,587, filed on Mar. 15, 2021, granted, now 12,245,416.
Prior Publication US 2023/0354576 A1, Nov. 2, 2023
Int. Cl. H10B 12/00 (2023.01); H01L 21/311 (2006.01); H01L 21/3213 (2006.01); H01L 21/762 (2006.01)
CPC H10B 12/053 (2023.02) [H01L 21/31116 (2013.01); H01L 21/31144 (2013.01); H01L 21/32136 (2013.01); H01L 21/32139 (2013.01); H01L 21/76224 (2013.01); H10B 12/34 (2023.02); H10B 12/488 (2023.02)] 9 Claims
OG exemplary drawing
 
1. A semiconductor structure, comprising:
a substrate comprising an isolation region, an active region adjacent to the isolation region, a first top surface, an isolation trench recessed into the first top surface and disposed in the isolation region, and a gate trench recessed into the first top surface and disposed in the active region;
a dielectric material deposited in a lower portion of the isolation trench, wherein the dielectric material has a second top surface below the first top surface;
a gate electrode material deposited in a lower portion of the gate trench, wherein the gate electrode material has a third top surface substantially at a same level as the second top surface; and
a gate conductive material deposited in an upper portion of the isolation trench to cover the dielectric material and deposited in an upper portion of the gate trench to cover the gate electrode material;
wherein the gate conductive material deposited in the upper portion of the isolation trench has a first gate conductive top surface coplanar with the first top surface of the substrate;
wherein the gate conductive material deposited in the upper portion of the gate trench has a second gate conductive top surface coplanar with the first top surface of the substrate.