US 12,267,607 B2
Image sensor with controlled SPAD avalanche
Tso-Sheng Tsai, Hsin-Chu County (TW)
Assigned to PIXART IMAGING INC., Hsin-Chu County (TW)
Filed by PixArt Imaging Inc., Hsin-Chu County (TW)
Filed on May 30, 2024, as Appl. No. 18/677,949.
Application 18/677,949 is a division of application No. 17/943,579, filed on Sep. 13, 2022, granted, now 12,028,636.
Application 17/378,843 is a division of application No. 16/872,626, filed on May 12, 2020, granted, now 11,102,439.
Application 16/872,626 is a division of application No. 16/258,673, filed on Jan. 28, 2019, granted, now 10,715,756.
Application 16/872,626 is a division of application No. 16/258,673, filed on Jan. 28, 2019, granted, now 10,715,756.
Application 17/943,579 is a continuation in part of application No. 17/378,843, filed on Jul. 19, 2021, granted, now 11,575,854.
Application 17/943,579 is a continuation in part of application No. 17/883,746, filed on Aug. 9, 2022, abandoned.
Application 17/883,746 is a continuation in part of application No. 17/378,843, filed on Jul. 19, 2021, granted, now 11,575,854.
Prior Publication US 2024/0314465 A1, Sep. 19, 2024
Int. Cl. H04N 25/75 (2023.01); H01L 27/146 (2006.01); H01L 31/107 (2006.01); H04N 25/76 (2023.01)
CPC H04N 25/75 (2023.01) [H01L 27/14612 (2013.01); H01L 27/14643 (2013.01); H04N 25/76 (2023.01); H01L 31/107 (2013.01)] 10 Claims
OG exemplary drawing
 
1. An image sensor, comprising:
a pixel array, comprising a plurality of pixel circuits arranged in a matrix, each of the pixel circuits comprising:
an avalanche diode, having an anode connected to a first node;
an enable transistor, a source of the enable transistor connected to the first node, and a gate of the enable transistor configured to receive an enable signal, which is configured to determine multiple enabling periods for turning off the enable transistor within an exposure period of the pixel circuit;
a first switch transistor, a drain of the first switch transistor connected to the first node, a gate of the first switch transistor configured to receive a first reset signal, and a source of the first switch transistor connected to a ground voltage;
an exposure transistor, a source of the exposure transistor connected to the first node, a drain of the exposure transistor connected to a second node, and a gate of the exposure transistor configured to receive an exposure signal for turning on the exposure transistor corresponding to the multiple enabling periods within the exposure period;
a reset transistor, a gate of the reset transistor receiving a second reset signal, a drain of the reset transistor connected to a third node, and a source of the reset transistor connected to the ground voltage;
a control transistor, a gate of the control transistor connected to the second node, and a source of the control transistor connected to the third node;
a pull down transistor, a gate of the pull down transistor connected to the third node, and a source of the pull down transistor connected to the ground voltage; and
a second switch transistor, a gate of the second switch transistor configured to receive a readout signal, a source of the second switch transistor connected to a drain of the pull down transistor, and a drain of the second switch transistor configured to generate an output voltage.