US 12,267,514 B2
Video decoding apparatus and method
Hwayong Oh, Seoul (KR)
Assigned to Samsung Electronics Co., Ltd., Gyeonggi-do (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Apr. 15, 2022, as Appl. No. 17/721,707.
Claims priority of application No. 10-2021-0102017 (KR), filed on Aug. 3, 2021.
Prior Publication US 2023/0040891 A1, Feb. 9, 2023
Int. Cl. H04N 19/44 (2014.01); G06F 9/50 (2006.01); H04N 19/15 (2014.01); H04N 19/184 (2014.01); H04N 19/42 (2014.01)
CPC H04N 19/44 (2014.11) [G06F 9/5027 (2013.01); H04N 19/15 (2014.11); H04N 19/184 (2014.11); H04N 19/42 (2014.11)] 20 Claims
OG exemplary drawing
 
1. A video decoding apparatus comprising:
a central processing unit (CPU) including a reduced instruction set computer (RISC) that drives firmware and register sets each including a plurality of registers configured to store data, the CPU configured to parse first header data included in a first frame of a first bit-stream of an input bit-stream and configure a first register set of the register sets included in the CPU based on the parsed first header data; and
a hardware decoder configured to decode the first bit-stream based on input parameters obtained through the first register set,
wherein while the hardware decoder decodes the first bit-stream corresponding to the first frame of the input-bit stream, the CPU is configured to parse second header data included in a second bit-stream of the input bit-stream of a second frame subsequent to the first frame such that decoding of the first bit-stream and parsing of the second header data included in the second bit-stream are performed in parallel by different ones of the hardware decoder and the CPU.