CPC H04N 19/132 (2014.11) [H04L 65/70 (2022.05); H04N 19/172 (2014.11); H04N 19/188 (2014.11); H04N 19/46 (2014.11)] | 20 Claims |
1. A video decoding device comprising:
a communication interface configured to receive a compressed video bitstream including a decoder configuration record; and
a processor operably coupled to the communication interface, the processor configured to:
determine, based on a frame width value and a frame height value in the decoder configuration record, whether largest values for a frame width and a frame height for the compressed video bitstream are indicated by the frame width value and frame height value in the decoder configuration record;
when the largest values for the frame width and the frame height are indicated by the frame width value and the frame height value in the decoder configuration record, decode the compressed video bitstream based on the frame width value and the frame height value in the decoder configuration record; and
when the largest values for the frame width and the frame height are not indicated by the frame width value and the frame height value in the decoder configuration record:
determine, based on a sequence parameter set (SPS)_in_stream value in the decoder configuration record, whether an SPS stored in a file for the compressed video bitstream indicates the largest values of the frame width and the frame height and whether the compressed video bitstream contains an additional SPS, wherein the SPS is included in an array of network abstraction layer (NAL) units of the decoder configuration record and the additional SPS is not included in the array of NAL units of the decoder configuration record;
when the compressed video bitstream contains the additional SPS that is not included in the array of NAL units of the decoder configuration record, determine a frame width value and a frame height value from the additional SPS; and
decode the compressed video bitstream based on the frame width value and the frame height value from the additional SPS.
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