CPC H04N 19/13 (2014.11) [H04N 19/176 (2014.11); H04N 19/46 (2014.11); H04N 19/70 (2014.11); H04N 19/91 (2014.11)] | 2 Claims |
1. A decoder comprising:
circuitry; and
memory coupled to the circuitry, wherein
in both of a first type of residual decoding where an inverse orthogonal transform is applied to a current block and a second type of residual decoding where the inverse orthogonal transform is skipped for the current block, wherein a first syntax used for the first type of residual decoding is different from a second syntax used for the second type of residual decoding,
when a restriction on a number of Context-based Adaptive Binary Arithmetic Coding (CABAC) processes allows CABAC decoding of a set of a plurality of coefficient information flags, each coefficient information flag relating to a coefficient included in the current block, the circuitry:
decodes the plurality of coefficient information flags by CABAC decoding; and
when the restriction on the number of CABAC processes does not allow the CABAC decoding of the set of the plurality of coefficient information flags, the circuitry:
skips the CABAC decoding of the plurality of coefficient information flags; and
the circuitry decodes a remainder value of the coefficient with Golomb-Rice decoding when the plurality of coefficient information flags are decoded; and
the circuitry decodes a value of the coefficient with the Golomb-Rice decoding when the plurality of coefficient information flags are not decoded,
wherein in the second type of residual decoding, the circuitry decodes a plurality of absolute value flags, each absolute value flag relating to an absolute value of the coefficient after decoding the plurality of coefficient information flags and before decoding the remainder value of the coefficient.
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