US 12,267,409 B2
Increased data integrity for authenticated encryption algorithms
David Joseph Clinton, Coopersburg, PA (US); and Patrick Bailey, Port Coquitlam (CA)
Assigned to Microchip Technology Incorporated, Chandler, AZ (US)
Filed by Microchip Technology Incorporated, Chandler, AZ (US)
Filed on Jun. 11, 2021, as Appl. No. 17/304,011.
Claims priority of provisional application 62/705,194, filed on Jun. 15, 2020.
Prior Publication US 2021/0391978 A1, Dec. 16, 2021
Int. Cl. H04L 9/06 (2006.01); G06F 11/10 (2006.01); G06F 13/40 (2006.01); G06F 13/42 (2006.01)
CPC H04L 9/0637 (2013.01) [G06F 11/1004 (2013.01); G06F 13/4027 (2013.01); G06F 13/4282 (2013.01); H04L 9/0631 (2013.01); G06F 2213/0026 (2013.01)] 16 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a processor configured to:
generate a receiver modified block of data at least partially responsive to adding an error detecting code to a block of data, the receiver modified block of data including the error detecting code;
generate a receiver authentication code at least partially responsive to the receiver modified block of data; and
generate an indication of a difference between the receiver authentication code and a transmitter authentication code.