US 12,267,303 B2
Input/output system applied to network security defense system
Lei He, Zhengzhou (CN); Jiangxing Wu, Zhengzhou (CN); Qinrang Liu, Zhengzhou (CN); Ke Song, Zhengzhou (CN); Shuai Wei, Zhengzhou (CN); Jianliang Shen, Zhengzhou (CN); Libo Tan, Zhengzhou (CN); Yu Li, Zhengzhou (CN); Quan Ren, Zhengzhou (CN); Jun Zhou, Zhengzhou (CN); Min Fu, Zhengzhou (CN); Weili Zhang, Zhengzhou (CN); Ruihao Ding, Zhengzhou (CN); and Yiwei Guo, Zhuhai (CN)
Assigned to CHINA NATIONAL DIGITAL SWITCHING SYSTEM ENGINEERING & TECHNOLOGICAL R&D CENTER, Zhengzhou (CN); and PURPLE MOUNTAIN LABORATORIES, Nanjing (CN)
Appl. No. 17/789,082
Filed by CHINA NATIONAL DIGITAL SWITCHING SYSTEM ENGINEERING & TECHNOLOGICAL R&D CENTER, Zhengzhou (CN); and PURPLE MOUNTAIN LABORATORIES, Nanjing (CN)
PCT Filed Jun. 7, 2021, PCT No. PCT/CN2021/098596
§ 371(c)(1), (2) Date Jun. 24, 2022,
PCT Pub. No. WO2021/249335, PCT Pub. Date Dec. 16, 2021.
Claims priority of application No. 202010519102.X (CN), filed on Jun. 9, 2020.
Prior Publication US 2023/0039521 A1, Feb. 9, 2023
Int. Cl. H04L 9/40 (2022.01); H04L 1/00 (2006.01)
CPC H04L 63/0281 (2013.01) [H04L 1/0061 (2013.01)] 8 Claims
OG exemplary drawing
 
1. An input-output system applicable in a network security defense system, the input-output system comprising a structural encoding unit and an error correction decoding unit, wherein:
the structural encoding unit comprises an input branching processor and an input proxy processor, wherein the input branching processor is configured for message replication and distribution, the input branching processor is verified as having no backdoor, and is configured for erasing a memory of generalized disturbance;
the error correction decoding unit comprises an output selecting processor, an output proxy processor, an arbitration branching processor, an arbitration proxy processor and a voting processor, wherein:
the arbitration branching processor is configured to replicate and distribute data,
the voting processor is configured to vote,
the output selecting processor is configured to select, based on a voting result of the voting processor, an output result from processing results of the output proxy processor,
the output selecting processor, the arbitration branching processor and the voting processor are verified as having no backdoor and have the memory erasure function, and
at least the output proxy processor and the arbitration proxy processor are set up with a dynamically heterogeneous redundancy mechanism,
wherein any one of the input branching processor, the output selecting processor, the arbitration branching processor, and the voting processor serves as a target processor,
the target processor is configured with a non-random disturbance memory erasure mechanism,
wherein the target processor is further configured with a redundancy and replacement mechanism, wherein
the redundancy and replacement mechanism enable the target processor to erase a memory of random disturbance; and
the non-random disturbance memory erasure mechanism comprises at least one of program curing, program tamper resistance, data initialization, and data tamper resistance.