US 12,267,210 B2
Adapting forward error correction (FEC) or link parameters for improved post-FEC performance
Pervez Mirza Aziz, Dallas, TX (US); Vishnu Balan, Saratoga, CA (US); and Rohit Rathi, Milpitas, CA (US)
Assigned to NVIDIA Corporation, Santa Clara, CA (US)
Filed by NVIDIA Corporation, Santa Clara, CA (US)
Filed on Feb. 21, 2023, as Appl. No. 18/112,406.
Claims priority of provisional application 63/434,753, filed on Dec. 22, 2022.
Prior Publication US 2024/0214134 A1, Jun. 27, 2024
Int. Cl. H04L 41/0823 (2022.01); H03M 13/35 (2006.01); H04L 1/00 (2006.01); H04L 1/20 (2006.01)
CPC H04L 41/0823 (2013.01) [H03M 13/353 (2013.01); H04L 41/0836 (2013.01); H04L 1/0045 (2013.01); H04L 1/0071 (2013.01); H04L 1/203 (2013.01)] 23 Claims
OG exemplary drawing
 
1. A communication system comprising:
a receiver circuit;
a Forward Error Correction (FEC) circuit operatively coupled to the receiver circuit; and
a controller operatively coupled to the receiver circuit and the FEC circuit, wherein the controller is to:
receive FEC symbol error data from the FEC circuit;
determine, using the FEC symbol error data, a post-FEC correlated performance metric indicative of an estimated post-FEC bit error rate (BER) of the FEC circuit, wherein the post-FEC correlated performance metric is derived from a comparison of a measured FEC codeword histogram to a target histogram; and
adjust, based on the post-FEC correlated performance metric, at least one of a FEC parameter of the FEC circuit or a link parameter of the receiver circuit.