| CPC H04L 25/03057 (2013.01) [H03L 7/00 (2013.01); H03L 7/0807 (2013.01); H04L 7/0087 (2013.01); H04L 7/033 (2013.01); H04L 25/03038 (2013.01); H04L 25/085 (2013.01)] | 20 Claims |

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1. An integrated circuit comprising:
a signal node on the integrated circuit, to receive an incoming signal from a conductive path, the incoming signal carrying a sequence of data symbols;
a continuous time linear equalizer coupled to the signal node, to receive from the signal node a first signal which is dependent on the incoming signal, and to responsively generate an equalized output;
circuitry to generate a timing signal dependent on the equalized output; and
circuitry coupled to the signal node, to receive from the signal node a second signal which is dependent on the incoming signal, and to recover the data symbols of the sequence dependent on sampling a voltage of the second signal, wherein the second signal is not dependent on the continuous time linear equalizer, and wherein the recovery of the data symbols is dependent on the timing signal.
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