US 12,267,182 B2
Receiver synchronization
Raghu Ganesan, Bengaluru (IN); Saravanakkumar Radhakrishnan, Aruppukottai (IN); and Gaurav Aggarwal, Delhi (IN)
Assigned to Texas Instruments Incorporated, Dallas, TX (US)
Filed by Texas Instruments Incorporated, Dallas, TX (US)
Filed on Mar. 6, 2023, as Appl. No. 18/117,511.
Application 18/117,511 is a continuation of application No. 17/082,208, filed on Oct. 28, 2020, granted, now 11,601,302.
Claims priority of application No. 202041010827 (IN), filed on Mar. 13, 2020.
Prior Publication US 2023/0208675 A1, Jun. 29, 2023
Int. Cl. H04L 12/40 (2006.01); H04L 25/03 (2006.01)
CPC H04L 12/40039 (2013.01) [H04L 25/03267 (2013.01)] 22 Claims
OG exemplary drawing
 
10. A receiver circuit, comprising:
a feedback loop including a circuit, the circuit including a first and second registers; and
a sequencer coupled to the circuit of the feedback loop, the sequencer configured to:
cause the feedback loop to transition to a lower power state;
responsive to an error signal being below a threshold value, cause the first register to store an updated value for the feedback loop; and
responsive to a detected wake-up event, cause the updated value to be stored into the second register.