US 12,267,153 B2
Frame scheduling based on an estimated direct memory access (DMA) latency and apparatus for time aware frame scheduling
Mark Andrew Schellhorn, Ottawa (CA); Bernard Francois St-Denis, Ottawa (CA); and John Pillar, Ottawa (CA)
Assigned to NXP B.V., Eindhoven (NL)
Filed by NXP B.V., Eindhoven (NL)
Filed on Apr. 22, 2022, as Appl. No. 17/660,222.
Prior Publication US 2023/0344539 A1, Oct. 26, 2023
Int. Cl. G06F 13/28 (2006.01); H04J 3/06 (2006.01)
CPC H04J 3/0667 (2013.01) [G06F 13/287 (2013.01); H04J 3/0697 (2013.01)] 15 Claims
OG exemplary drawing
 
1. A method for transmitting a frame in a network station, the method comprising:
scheduling the frame for transmission at a transmit time based on a first clock;
issuing a request to a direct memory access (DMA) circuit to retrieve the frame from a system memory;
determining an advance time offset associated with the first clock based on an estimated DMA latency of the DMA circuit;
providing the frame retrieved by the DMA circuit to a staging circuit;
determining that a time of a second clock reaches the transmit time of the frame in the staging circuit, wherein a time of the first clock is ahead of a time of the second clock by the advance time offset; and
transmitting the frame at the transmit time based on the determination that the time of the second clock reaches the transmit time; wherein the estimated DMA latency is based on measuring a respective DMA latency to retrieve a plurality of data units from the system memory in a window of time and combining the DMA latency measurements; wherein combining the DMA latency measurements comprises averaging the DMA latency measurements; wherein the averaging the DMA latency measurements comprises weighing the DMA latency measurements by a weighting function in the average; and, wherein the weighting function comprises weighing older measurements of DMA latencies less than recent measurements of DMA latencies in the average.