US 12,267,152 B2
Synchronization circuit and synchronization chip
Fei Luo, Beijing (CN); and Weiwei Wang, Beijing (CN)
Assigned to Stream Computing Inc., Beijing (CN)
Filed by Stream Computing Inc., Beijing (CN)
Filed on Jan. 28, 2022, as Appl. No. 17/587,773.
Application 17/587,773 is a continuation of application No. PCT/CN2019/102269, filed on Aug. 23, 2019.
Prior Publication US 2022/0149963 A1, May 12, 2022
Int. Cl. H04J 3/06 (2006.01)
CPC H04J 3/0635 (2013.01) 20 Claims
OG exemplary drawing
 
1. A synchronization circuit, comprising M group synchronization signal generating circuits and a node synchronization signal generating circuit, M being a positive integer, wherein
an input terminal of each group synchronization signal generating circuit in the M group synchronization signal generating circuits is configured to connect to N nodes, N being a positive integer, and N being greater than or equal to M;
an output terminal of each group synchronization signal generating circuit in the M group synchronization signal generating circuits is connected to the node synchronization signal generating circuit;
an output terminal of the node synchronization signal generating circuit is configured to connect to the N nodes;
the group synchronization signal generating circuit is configured to generate a synchronization indication signal; and
the node synchronization signal generating circuit is configured to generate a synchronization signal based on the synchronization indication signal generated by the group synchronization signal generating circuit,
wherein each group synchronization signal generating circuit in the M group synchronization signal generating circuits comprises a node synchronization indicator, a synchronization ready signal generator, and a group node synchronization indication signal generator;
the node synchronization indicator is configured to indicate to-be-synchronized nodes in the N nodes;
the synchronization ready signal generator is configured to generate a synchronization ready signal when each node in the to-be-synchronized nodes is ready for synchronization;
the group node synchronization indication signal generator is configured to generate the synchronization indication signal based on the synchronization ready signal;
the synchronization ready signal generator comprises a shield and a synchronization determiner;
the shield is configured to receive synchronization ready indication signals from the N nodes, and generate an output signal according to indication of the node synchronization indicator; and
the synchronization determiner is configured to determine, according to the output signal of the shield, whether each node in the to-be-synchronized nodes is ready for synchronization, and generate the synchronization ready signal when it is determined that each node in the to-be-synchronized nodes is ready for synchronization.