CPC H04B 10/541 (2013.01) [H04J 14/08 (2013.01); H04L 27/34 (2013.01)] | 8 Claims |
1. A communication apparatus comprising:
at least one memory storing instructions; and
at least one processor configured to execute the instructions to:
transmit a plurality of types of quadrature amplitude-modulated signals;
add error correction codes to the quadrature amplitude-modulated signals; and
change the number of bits of the error correction code according to the type of the quadrature amplitude-modulated signal, and
change the number of bits of the error correction code in such a way that margins in regard to performance from the reception Q-value as transmission quality at an OSNR condition of each of the quadrature amplitude-modulated signals to a FEC correction limit are substantially equal to each other,
wherein the FEC correction limit is a maximum value of a bit error rate before FEC coding, and
wherein the maximum value satisfies the requirement that the Q value≥17 dB after the FEC coding.
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