US 12,267,080 B2
Clock frequency limiter
Jose A. Tierno, Menlo Park, CA (US); and Ajay M. Rao, San Jose, CA (US)
Assigned to Apple Inc., Cupertino, CA (US)
Filed by Apple Inc., Cupertino, CA (US)
Filed on May 15, 2024, as Appl. No. 18/664,811.
Application 18/664,811 is a continuation of application No. 17/664,364, filed on May 20, 2022, granted, now 12,021,538.
Prior Publication US 2024/0305303 A1, Sep. 12, 2024
Int. Cl. H03L 7/083 (2006.01); H03L 7/085 (2006.01); H03L 7/099 (2006.01)
CPC H03L 7/083 (2013.01) [H03L 7/085 (2013.01); H03L 7/0991 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a front-end circuit configured to generate an equalized signal using a plurality of signals that encode a serial data stream that includes a plurality of data symbols;
a clock generator circuit configured to generate a clock signal using a plurality of samples of the equalized signal; and
a measurement circuit configured to:
monitor a frequency of the clock signal; and
in response to a determination that the frequency of the clock signal exceeds a threshold frequency, activate an indication signal, wherein the threshold frequency is set at a level that causes a response to a frequency runaway condition caused by interruption of the serial data stream; and
wherein the clock generator circuit is further configured, in response to activation of the indication signal, to adjust the frequency of the clock signal to a particular frequency.