US 12,267,079 B2
Clock and data recovery device
Young Jae Chang, Seoul (KR); Sung Ryong Lee, Seongnam-Si (KR); and Jae Sam Shim, Seoul (KR)
Assigned to SILICON MITUS, INC., Seongnam-Si (KR); and Hangzhou Silicon-Magic Semiconductor Technology Co., Ltd., Hangzhou (CN)
Filed by SILICON MITUS, INC., Seongnam-Si (KR); and Hangzhou Silicon-Magic Semiconductor Technology Co., Ltd., Hangzhou (CN)
Filed on Jun. 30, 2023, as Appl. No. 18/345,872.
Prior Publication US 2024/0072811 A1, Feb. 29, 2024
Int. Cl. H03L 7/081 (2006.01); H03L 7/089 (2006.01); H04L 7/033 (2006.01)
CPC H03L 7/0816 (2013.01) [H03L 7/089 (2013.01); H04L 7/033 (2013.01)] 11 Claims
OG exemplary drawing
 
1. A clock and data recovery device for reducing loop delay in a bang-bang loop comprising:
an equalizer that compensates for channel loss of input data;
a phase detector that compares a data output from the equalizer with a clock fed back from a voltage controlled oscillator and outputs an up signal and a down signal;
a charge pump that operates according to the up signal and the down signal and outputs a control signal;
a loop filter that removes high-frequency components included in the control signal output from the charge pump;
the voltage controlled oscillator that changes a frequency of the clock and outputs a clock with changed frequency according to the control signal from which the high-frequency components have been removed; and
a data phase adjuster that synchronizes the clock output from the voltage controlled oscillator and the data output from the equalizer by adjusting a phase of the data output from the equalizer by receiving the up signal and the down signal output from the phase detector.