US 12,267,078 B2
Synchronizing digital device
Matteo Quartiroli, Certosa di Pavia (IT); Alessandro Mecchia, Vimercate (IT); and Paolo Pesenti, Senago (IT)
Assigned to STMICROELECTRONICS S.r.l., Agrate Brianza (IT)
Filed by STMICROELECTRONICS S.r.l., Agrate Brianza (IT)
Filed on Jul. 14, 2023, as Appl. No. 18/352,581.
Claims priority of application No. 102022000016557 (IT), filed on Aug. 3, 2022.
Prior Publication US 2024/0048144 A1, Feb. 8, 2024
Int. Cl. H03L 7/081 (2006.01); H03L 7/099 (2006.01)
CPC H03L 7/0814 (2013.01) [H03L 7/0992 (2013.01)] 21 Claims
OG exemplary drawing
 
1. A device, comprising:
a local oscillator, which, in operation, generates a local clock signal having a local clock frequency;
an all-digital phase locked loop (ADPLL) coupled to the local oscillator, wherein ADPLL, in operation, generates a sampling control signal, the ADPLL including:
a phase-error detector, which, in operation, generates a phase error signal based on a loop clock signal and a received reference signal;
a digital filter coupled to the phase-error detector, wherein the digital filter, in operation, generates a signal indicative of a frequency ratio between a frequency of the reference clock signal and the local clock frequency based on the phase error signal; and
a sigma-delta modulator coupled to the digital filter, wherein the sigma-delta modulator, in operation, generates a modulated signal based on the signal indicative of the frequency ratio generated by the digital filter, and the sampling control signal is based on the modulated signal;
digital signal generating circuitry coupled to the local oscillator, wherein the digital signal generating circuitry, in operation, generates digital signals;
sampling circuitry, coupled to the digital signal generating circuitry and to the ADPLL, wherein the sampling circuitry, in operation, samples digital signals generated by the digital signal generating circuitry at a sampling frequency which is a function of the sampling control signal; and
an interface coupled to the sampling circuitry, wherein the interface, in operation, outputs sampled data signals.