US 12,267,076 B2
Signal receiving apparatus, clock and data recovery circuit and clock and data recovery method thereof
Chi-Kung Kuan, Hsinchu (TW); Li-Jun Gu, Suzhou (CN); Peng Huang, Suzhou (CN); Chia-Peng Fang, Hsinchu (TW); and Zhi-Yong Tang, Suzhou (CN)
Assigned to REALTEK SEMICONDUCTOR CORPORATION, Hsinchu (TW)
Filed by REALTEK SEMICONDUCTOR CORPORATION, Hsinchu (TW)
Filed on Aug. 25, 2023, as Appl. No. 18/238,023.
Prior Publication US 2025/0070786 A1, Feb. 27, 2025
Int. Cl. H03L 7/08 (2006.01); H03L 7/091 (2006.01); H04L 27/227 (2006.01)
CPC H03L 7/0807 (2013.01) [H03L 7/091 (2013.01); H04L 27/2275 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A clock and data recovery (CDR) circuit, comprising:
a sampling circuit configured to perform a burst mode over-sampling on an input analog data signal according to a sampling timing in a burst mode to generate a plurality of over-sampling results;
a selection circuit configured to determine neighboring two of the over-sampling results having opposite logic states in the burst mode to accordingly select a plurality of data edge sampling results and a plurality of data center sampling results interlaced with each other and having a same time period with the input analog data signal from the over-sampling results to output a plurality of output sampling results;
a phase detection circuit configured to perform phase detection according to the output sampling results to generate a phase locking direction; and
a phase adjusting circuit configured to adjust the sampling timing of the sampling circuit according to the phase locking direction to track the input analog data signal.