US 12,267,075 B2
Low-power inter-die communication using delay lines
Sameer Wadhwa, San Diego, CA (US); and Lennart Karl-Axel Mathe, San Diego, CA (US)
Assigned to QUALCOMM INCORPORATED, San Diego, CA (US)
Filed by QUALCOMM Incorporated, San Diego, CA (US)
Filed on May 25, 2023, as Appl. No. 18/323,942.
Application 18/323,942 is a continuation of application No. 17/887,282, filed on Aug. 12, 2022, granted, now 11,695,400.
Prior Publication US 2024/0056067 A1, Feb. 15, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H03K 5/00 (2006.01); H03K 5/14 (2014.01); H03K 5/1534 (2006.01); H03K 5/19 (2006.01); H03K 5/15 (2006.01); H03K 5/1536 (2006.01)
CPC H03K 5/14 (2013.01) [H03K 5/1534 (2013.01); H03K 5/19 (2013.01); H03K 5/15033 (2013.01); H03K 5/1504 (2013.01); H03K 5/1536 (2013.01)] 28 Claims
OG exemplary drawing
 
1. A serializer, comprising:
a delay line including a plurality of pulse generation circuits, each pulse generation circuit being configured to provide a pulse in a corresponding one of N delay line signals generated by the delay line, where Nis an integer greater than 1 and where each pulse generated by the plurality of pulse generation circuits has a duration that is 1/Nth of a period of a transmit clock signal received at an input of the delay line; and
a plurality of buffers coupled to a data source, each buffer being enabled by pulses in a corresponding one of the N delay line signals and configured to couple a signal representing an associated bit from the data source to a data line of a serial communication link when enabled by the pulses in the corresponding delay line signal,
wherein each pulse generation circuit includes a pulse control circuit configured to terminate pulses in its corresponding delay line signal at the leading edge of a pulse generated by a next-in-line pulse generation circuit.