US 12,267,074 B2
Dynamic D flip-flop with an inverted output
Wenbo Tian, Guangdong (CN); Zhijun Fan, Guangdong (CN); Haifeng Guo, Guangdong (CN); and Zuoxing Yang, Guangdong (CN)
Assigned to SHENZHEN MICROBT ELECTRONICS TECHNOLOGY CO., LTD., Guangdong (CN)
Appl. No. 18/002,302
Filed by SHENZHEN MICROBT ELECTRONICS TECHNOLOGY CO., LTD., Guangdong (CN)
PCT Filed Apr. 16, 2021, PCT No. PCT/CN2021/087622
§ 371(c)(1), (2) Date Dec. 19, 2022,
PCT Pub. No. WO2021/258824, PCT Pub. Date Dec. 30, 2021.
Claims priority of application No. 202010575350.6 (CN), filed on Jun. 22, 2020.
Prior Publication US 2023/0238947 A1, Jul. 27, 2023
Int. Cl. H03K 3/3562 (2006.01); H03K 3/012 (2006.01); H03K 3/356 (2006.01)
CPC H03K 3/35625 (2013.01) [H03K 3/012 (2013.01); H03K 3/356008 (2013.01)] 11 Claims
OG exemplary drawing
 
1. A dynamic D flip-flop with an inverted output, comprising:
an input end configured for receiving input data from external to the dynamic D flip-flop;
an output end configured for providing output data in response to the input data;
a clock signal end configured for receiving clock signals;
a first latch configured for latching the input data from the input end and carrying out, under the control of the clock signals, an inverted transmission on the input data;
a second latch configured for latching the data from the first latch and carrying out, under the control of the clock signals, an inverted transmission on the data latched by the first latch; and
an inverter configured for carrying out an inverted output on the data received from the second latch,
wherein the first latch, the second latch, and the inverter are sequentially connected in series between the input end and the output end, the dynamic D flip-flop with an inverted output does not have an inverter between the input end and the first latch, and the first latch is a tri-state inverter whose input end directly provides the input end of the dynamic D flip-flop with an inverted output,
wherein the dynamic D flip flop comprises a first node at an input end of the second latch and a second node at an output end of the second latch, and the clock signals comprise a first clock signal and a second clock signal, the first clock signal being inverted with respect to the second clock signal,
wherein the second latch is configured for:
in a case where one of the first and second clock signals is at a low level and another one of the first and second clock signals is at a high level, inverting the data at the first node and outputting the inverted data to the second node such that the data at the second node is overwritten; and
in a case where the one of the first and second clock signals is at a high level and the other one of the first and second clock signals is at a low level, preventing the data at the first node from passing therethrough such that the data at the second node is latched at the second node and maintains an original state.