CPC H03H 9/72 (2013.01) [H10N 30/802 (2023.02)] | 19 Claims |
1. A multiplexer/demultiplexer comprising:
unit cells arranged in a lattice, each of the unit cells comprising:
a topological-insulative material;
a first piezoelectric patch; and
a second piezoelectric patch;
a first domain comprising a first portion of the unit cells;
a second domain comprising a second portion of the unit cells;
a third domain comprising a third portion of the unit cells; and
a controller configured to:
apply a negative capacitance to the first piezoelectric patches in the first portion of the unit cells;
apply a negative capacitance to the second piezoelectric patches in the second portion of the unit cells; and
alternately apply a negative capacitance to the first and second piezoelectric patches, respectively, in the third portion of the unit cells.
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