US 12,267,058 B1
Adaptive-bias MOS impedance for reduced-area RC filter
Yueh Chun Cheng, Cupertino, CA (US)
Assigned to Ambarella International LP, Santa Clara, CA (US)
Filed by Ambarella International LP, Santa Clara, CA (US)
Filed on Sep. 9, 2022, as Appl. No. 17/942,093.
Int. Cl. G05F 3/26 (2006.01); H03H 7/01 (2006.01)
CPC H03H 7/0153 (2013.01) [G05F 3/262 (2013.01)] 19 Claims
OG exemplary drawing
 
1. An adaptive-bias metal-oxide-semiconductor (MOS) device comprising:
a first terminal;
a second terminal;
a third terminal;
a first MOS device; and
a second MOS device, wherein
the first MOS device has a first width and a first gate length,
the second MOS device has a second width and a second gate length,
the first terminal is connected to a first source terminal of the first MOS device and a second source terminal of the second MOS device,
the second terminal is connected to a first drain terminal of the first MOS device, a first gate terminal of the first MOS device, and a second gate terminal of the second MOS device,
the third terminal is connected to a second drain terminal of the second MOS device, and
the first MOS device and the second MOS device are configured to operate in a sub-threshold operating region, wherein a first gate-source voltage of the first MOS device and a second gate-source voltage of the second MOS device are less than a first threshold voltage of the first MOS device and the first threshold voltage of the first MOS device is less than a second threshold voltage of the second MOS device.