US 12,267,053 B2
Differential amplifier, semiconductor device and offset cancellation method
Koichi Takeda, Tokyo (JP); Takahiro Shimoi, Tokyo (JP); Masaya Nakano, Tokyo (JP); Hidenori Mitani, Tokyo (JP); and Yoshinobu Kaneda, Tokyo (JP)
Assigned to RENESAS ELECTRONICS CORPORATION, Tokyo (JP)
Filed by RENESAS ELECTRONICS CORPORATION, Tokyo (JP)
Filed on Oct. 13, 2022, as Appl. No. 17/965,308.
Claims priority of application No. 2021-181109 (JP), filed on Nov. 5, 2021.
Prior Publication US 2023/0145662 A1, May 11, 2023
Int. Cl. H03F 1/02 (2006.01); H03F 3/45 (2006.01)
CPC H03F 3/45744 (2013.01) [H03F 3/45497 (2013.01); H03F 3/45511 (2013.01); H03F 3/45183 (2013.01); H03F 3/45475 (2013.01)] 13 Claims
OG exemplary drawing
 
1. A differential amplifier comprising:
a current source that is connected to a first power supply in which a suppliable current is a first current;
an active element pair that is connected to the current source, and amplifies a signal input to an input terminal pair to output an output signal pair;
a load element pair that is connected to a second power supply different in power supply voltage from the first power supply, the load element pair serving for outputting the output signal pair to an output terminal pair;
a capacitance element pair that is inserted between an external input terminal pair and the input terminal pair;
a switching element pair that performs an offset cancellation operation to charge the capacitance element pair such as to cause the capacitance element pair to generate a voltage by short-circuiting corresponding terminals between the output terminal pair and the input terminal pair, the voltage being obtained by converting an offset voltage of the input terminal pair into an input voltage; and
a current control circuit that controls a current suppliable by the current source to be a second current larger than the first current at a time of performing the offset cancellation operation.