| CPC H02P 27/085 (2013.01) [H02M 7/5395 (2013.01)] | 16 Claims |

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1. An integrated circuit (IC), comprising:
a pulse width modulation (PWM) generator configured to generate a first PWM signal;
a first counter having a first control input and a first reset input, the first control input configured to receive the first PWM signal, and the first reset input configured to receive a logical inverse of the first PWM signal, the first counter having a first counter output;
a second counter having a second control input and a second reset input, the second control input configured to receive the logical inverse of the first PWM signal, and the second reset input configured to receive the first PWM signal, the second counter having a second counter output;
a first logic circuit having a first logic circuit input and a second logic circuit input, the first logic circuit input coupled to the first counter output, and the second logic circuit input configured to receive the first PWM signal, the first logic circuit having a first logic circuit output configured to provide a second PWM signal; and
a second logic circuit having a third logic circuit input and a fourth logic circuit input, the third logic circuit input coupled to the second counter output, and the fourth logic circuit input configured to receive the logical inverse of the first PWM signal, the second logic circuit having a second logic circuit output configured to provide a third PWM signal.
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