US 12,266,927 B2
Electrostatic discharge (ESD) protection circuits using tunneling field effect transistor (TFET) and impact ionization MOSFET (IMOS) devices
Radhakrishnan Sithanandam, Greater Noida (IN)
Assigned to STMicroelectronics International N.V., Geneva (CH)
Filed by STMicroelectronics International N.V., Geneva (CH)
Filed on Jun. 8, 2023, as Appl. No. 18/207,493.
Application 18/207,493 is a continuation of application No. 17/222,352, filed on Apr. 5, 2021, granted, now 11,710,961.
Application 17/222,352 is a continuation of application No. 15/908,878, filed on Mar. 1, 2018, granted, now 10,998,721, issued on May 4, 2021.
Claims priority of provisional application 62/506,709, filed on May 16, 2017.
Claims priority of provisional application 62/478,302, filed on Mar. 29, 2017.
Prior Publication US 2023/0318287 A1, Oct. 5, 2023
Int. Cl. H02H 9/04 (2006.01); H01L 23/528 (2006.01); H01L 27/02 (2006.01); H01L 27/06 (2006.01); H01L 27/12 (2006.01); H01L 29/06 (2006.01); H01L 29/08 (2006.01); H01L 29/739 (2006.01); H01L 29/78 (2006.01); H01L 29/87 (2006.01); H01L 29/73 (2006.01); H01L 49/02 (2006.01)
CPC H02H 9/046 (2013.01) [H01L 23/528 (2013.01); H01L 27/0255 (2013.01); H01L 27/0262 (2013.01); H01L 27/0266 (2013.01); H01L 27/0635 (2013.01); H01L 27/1203 (2013.01); H01L 29/0649 (2013.01); H01L 29/0847 (2013.01); H01L 29/7391 (2013.01); H01L 29/7835 (2013.01); H01L 29/87 (2013.01); H01L 28/20 (2013.01); H01L 28/40 (2013.01); H01L 29/0653 (2013.01); H01L 29/73 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A circuit, comprising:
a first power supply line;
an input/output node;
a protection circuit having a first terminal electrically coupled to the input/output node and a second terminal electrically coupled to the first power supply line;
a silicon controlled rectifier (SCR) device having an anode terminal electrically coupled to the input/output node and a cathode terminal electrically coupled to the first power supply line, the SCR device having a first internal node; and
a first gate grounded impact ionization MOSFET (GGIMOS) device having a drain terminal electrically coupled to the internal node, a source terminal electrically coupled to the first power supply line and a gate terminal electrically coupled to the first power supply line.