| CPC H02H 9/046 (2013.01) [H03K 17/6872 (2013.01)] | 8 Claims |
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1. A circuit comprising:
a voltage division circuit electrically coupled to a voltage input terminal configured to receive a power signal to generate a detection signal at a voltage division terminal;
a first inverter circuit configured to receive and invert the detection signal to output an inverted detection signal;
a voltage boosting circuit comprising:
a first PMOS circuit and a first NMOS circuit electrically coupled in series through a first terminal between the voltage input terminal and a ground terminal, wherein the first PMOS circuit comprises a first PMOS control terminal electrically coupled to a second terminal and the first NMOS circuit comprises a first NMOS control terminal configured to receive the inverted detection signal;
a second PMOS circuit and a second NMOS circuit electrically coupled in series through the second terminal between the voltage input terminal and the ground terminal, wherein the second PMOS circuit comprises a second PMOS control terminal electrically coupled to the first terminal and the second NMOS circuit comprises a second NMOS control terminal configured to receive the detection signal, and the second PMOS circuit further comprises a plurality of P-type transistors electrically coupled in series; and
an N-type transistor electrically coupled between the first terminal and the ground terminal and comprising a third N-type transistor control terminal electrically coupled to the second terminal;
a second inverter circuit electrically coupled between the voltage input terminal and the ground terminal and configured to receive and invert an inverted boost detection signal from the second terminal to output a boost detection signal; and
an electrostatic discharge (ESD) circuit electrically coupled between the voltage input terminal and the ground terminal and configured to be activated according to the boost detection signal for discharging the voltage input terminal.
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