US 12,266,878 B2
Electrical interconnect with improved impedance
Daqiao Du, Lake Oswego, OR (US); Zhen Zhou, Chandler, AZ (US); Ismael Franco Núñez, Milwaukie, OR (US); and Gordon P. Melz, Beaverton, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Sep. 24, 2021, as Appl. No. 17/484,865.
Prior Publication US 2022/0013944 A1, Jan. 13, 2022
Int. Cl. H01R 13/00 (2006.01); H01R 12/71 (2011.01); H01R 13/05 (2006.01); H01R 13/11 (2006.01); H01R 43/00 (2006.01)
CPC H01R 13/052 (2013.01) [H01R 12/712 (2013.01); H01R 13/111 (2013.01); H01R 43/00 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus comprising:
an interconnect comprising:
a conductive core;
a first conductive layer connected to the conductive core and extending parallel to the conductive core towards a first end of the conductive core;
a second conductive layer connected to the conductive core and extending parallel to the conductive core towards a second end of the conductive core;
a first non-conductive layer between the conductive core and the first conductive layer; and
a second non-conductive layer between the first conductive layer and the second conductive layer.