US 12,266,847 B2
Semiconductor packages and manufacturing methods thereof
Yung-Ping Chiang, Hsinchu County (TW); Chao-Wen Shih, Hsinchu County (TW); Shou-Zen Chang, New Taipei (TW); Albert Wan, Hsinchu (TW); and Yu-Sheng Hsieh, New Taipei (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Dec. 24, 2023, as Appl. No. 18/395,617.
Application 18/395,617 is a continuation of application No. 17/874,252, filed on Jul. 26, 2022, granted, now 11,855,333.
Application 17/874,252 is a continuation of application No. 17/227,387, filed on Apr. 12, 2021, granted, now 11,515,618, issued on Nov. 29, 2022.
Application 17/227,387 is a continuation of application No. 16/858,743, filed on Apr. 27, 2020, granted, now 10,978,782, issued on Apr. 13, 2021.
Application 16/858,743 is a continuation of application No. 16/219,979, filed on Dec. 14, 2018, granted, now 10,636,713, issued on Apr. 28, 2020.
Application 16/219,979 is a continuation of application No. 15/235,106, filed on Aug. 12, 2016, granted, now 10,157,807, issued on Dec. 18, 2018.
Claims priority of provisional application 62/341,633, filed on May 26, 2016.
Prior Publication US 2024/0128635 A1, Apr. 18, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H01Q 1/22 (2006.01); H01L 21/56 (2006.01); H01L 21/768 (2006.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01); H01L 23/48 (2006.01); H01L 23/528 (2006.01); H01L 23/66 (2006.01); H01Q 1/38 (2006.01); H01Q 9/04 (2006.01); H01Q 21/06 (2006.01)
CPC H01Q 1/2283 (2013.01) [H01L 21/768 (2013.01); H01L 23/3107 (2013.01); H01L 23/3128 (2013.01); H01L 23/481 (2013.01); H01L 23/528 (2013.01); H01L 23/66 (2013.01); H01L 24/14 (2013.01); H01L 24/82 (2013.01); H01Q 1/38 (2013.01); H01Q 9/04 (2013.01); H01Q 21/065 (2013.01); H01L 21/568 (2013.01); H01L 2223/6627 (2013.01); H01L 2223/6677 (2013.01); H01L 2224/13024 (2013.01); H01L 2224/13111 (2013.01); H01L 2224/13113 (2013.01); H01L 2224/13116 (2013.01); H01L 2224/13139 (2013.01); H01L 2224/13147 (2013.01); H01L 2224/13155 (2013.01); H01L 2224/18 (2013.01); H01L 2924/1431 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor package, comprising:
a semiconductor chip, having a first side and a second side opposite to each other and comprising a connector protruding from the first side thereof;
an encapsulant, disposed around the semiconductor chip and in contact with the connector;
a first redistribution layer structure, disposed at the first side of the semiconductor chip and comprising a first conductive feature in contact with the connector of the semiconductor chip and a plurality of second conductive features laterally aside the first conductive feature, wherein the second conductive features are separated from the semiconductor chip by a polymer material of the first redistribution layer structure; and
a second redistribution layer structure, disposed at the second side of the semiconductor chip.