US 12,266,840 B2
Waveguide interconnects for semiconductor packages and related methods
Georgios Dogiamis, Chandler, AZ (US); Johanna Swan, Scottsdale, AZ (US); Adel Elsherbini, Tempe, AZ (US); Shawna Liff, Scottsdale, AZ (US); Beomseok Choi, Chandler, AZ (US); and Qiang Yu, Saratoga, CA (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Jun. 25, 2021, as Appl. No. 17/359,138.
Prior Publication US 2022/0416393 A1, Dec. 29, 2022
Int. Cl. H01P 3/16 (2006.01); H01L 23/538 (2006.01); H01L 23/66 (2006.01); H01L 25/065 (2023.01); H01P 1/208 (2006.01); H01P 5/107 (2006.01)
CPC H01P 3/16 (2013.01) [H01L 23/5384 (2013.01); H01L 23/66 (2013.01); H01L 25/0657 (2013.01); H01P 1/2088 (2013.01); H01P 5/107 (2013.01); H01L 2223/6627 (2013.01)] 22 Claims
OG exemplary drawing
 
1. A semiconductor package comprising:
a first semiconductor die;
a second semiconductor die; and
a substrate positioned between the first semiconductor die and the second semiconductor die, the substrate including:
a waveguide interconnect to provide a communication channel to carry an electromagnetic signal, the waveguide interconnect defined by a plurality of through substrate vias (TSVs), the TSVs in a pattern around at least a portion of the substrate to define a boundary of the communication channel.