US 12,266,769 B2
Semiconductor device and electronic device
Junpei Momo, Kanagawa (JP); Kazutaka Kuriki, Kanagawa (JP); Hiromichi Godo, Kanagawa (JP); and Shunpei Yamazaki, Tokyo (JP)
Assigned to SEMICONDUCTOR ENERGY LABORATORY CO., LTD., Kanagawa-ken (JP)
Filed by SEMICONDUCTOR ENERGY LABORATORY CO., LTD., Atsugi (JP)
Filed on Dec. 8, 2023, as Appl. No. 18/534,217.
Application 18/534,217 is a continuation of application No. 17/676,874, filed on Feb. 22, 2022, granted, now 11,848,429, issued on Dec. 19, 2023.
Application 17/676,874 is a continuation of application No. 17/019,700, filed on Sep. 14, 2020, granted, now 11,342,599, issued on May 24, 2022.
Application 17/019,700 is a continuation of application No. 16/360,065, filed on Mar. 21, 2019, granted, now 10,862,177, issued on Dec. 8, 2020.
Application 16/360,065 is a continuation of application No. 15/117,349, granted, now 10,290,908, issued on May 14, 2019, previously published as PCT/IB2015/050768, filed on Feb. 2, 2015.
Claims priority of application No. 2014-026312 (JP), filed on Feb. 14, 2014.
Prior Publication US 2024/0113346 A1, Apr. 4, 2024
Int. Cl. H01M 10/46 (2006.01); A61N 1/378 (2006.01); G06F 1/16 (2006.01); H01L 21/822 (2006.01); H01L 27/06 (2006.01); H01L 27/12 (2006.01); H01L 29/786 (2006.01); H01M 10/052 (2010.01); H01M 10/0525 (2010.01); H01M 10/0562 (2010.01); H01M 10/0585 (2010.01); H01M 10/42 (2006.01); H01M 10/613 (2014.01); H01M 10/623 (2014.01); H02J 50/20 (2016.01)
CPC H01M 10/46 (2013.01) [A61N 1/378 (2013.01); G06F 1/163 (2013.01); H01L 21/8221 (2013.01); H01L 27/0688 (2013.01); H01L 27/1218 (2013.01); H01L 27/1225 (2013.01); H01L 27/124 (2013.01); H01L 27/1251 (2013.01); H01L 29/78651 (2013.01); H01L 29/7869 (2013.01); H01M 10/052 (2013.01); H01M 10/0525 (2013.01); H01M 10/0562 (2013.01); H01M 10/0585 (2013.01); H01M 10/425 (2013.01); H01M 10/613 (2015.04); H01M 10/623 (2015.04); H02J 50/20 (2016.02); H01M 2220/30 (2013.01); H01M 2300/0071 (2013.01)] 4 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a first transistor over a first substrate;
a second transistor over the first substrate and the first transistor; and
a battery over the first substrate and the second transistor, the battery comprising a positive electrode current collector layer,
wherein a first gate insulating film of the first transistor is provided over a first channel region of the first transistor,
wherein a first gate electrode of the first transistor is provided over the first gate insulating film of the first transistor,
wherein a first insulating film is provided over the first gate electrode of the first transistor,
wherein a second gate electrode of the second transistor is provided over the first insulating film,
wherein a second insulating film is provided over the second gate electrode of the second transistor,
wherein a second channel region of the second transistor is provided over the second insulating film,
wherein a third insulating film is provided over the second channel region of the second transistor,
wherein the positive electrode current collector layer is provided over and in contact with the third insulating film,
wherein one of a source region and a drain region of the first transistor is electrically connected to one of a source electrode and a drain electrode of the second transistor, and
wherein the other of the source electrode and the drain electrode of the second transistor is electrically connected to the positive electrode current collector layer.