US 12,266,729 B2
Angled etch to enable tin removal from selected sidewalls
Nafees A. Kabir, Portland, OR (US); Shriram Shivaraman, Hillsboro, OR (US); Seung Hoon Sung, Portland, OR (US); and Uygar E. Avci, Portland, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Sep. 24, 2021, as Appl. No. 17/485,162.
Prior Publication US 2023/0102900 A1, Mar. 30, 2023
Int. Cl. H01L 21/4763 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 29/786 (2006.01)
CPC H01L 29/7869 (2013.01) [H01L 21/47635 (2013.01); H01L 29/66969 (2013.01); H01L 29/785 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method of fabricating an integrated circuit structure, comprising:
depositing an oxide insulator layer over a substrate having fins;
forming a gate trench within the oxide insulator layer with the fins extending above a surface of the oxide insulator layer within the gate trench;
depositing semiconducting oxide material to conformally cover the oxide insulator layer, including on top surfaces and sidewalls of both the gate trench and the fins;
depositing a gate material to conformally cover the semiconducting oxide material, including on top surfaces and sidewalls of both the gate trench and the fins; and
performing an angled etch to remove the gate material selective to the semiconducting oxide material from sidewalls of the gate trench, but not from sidewalls of the fins.